EEL6935: HW#4

Due Thursday, November 14, 1996. This could be your final homework assignment of the semester. By the end of this assignment, you should have a complete functional chip suitable for fabrication. I will be providing you more information about S-EDIT, TSPICE and the padrame next week. Note, you do not need to use the Tanner toolset, Magic+PSPICE or CADENCE can also perform these same functions.

LVS, done by October 31

A1

Layout a follower integrator cell using your transamp layout from the last assignment.

A2

Draw a schematic of the follower integrator in S-EDIT.

A3

Do a LVS (Layout vs. schematic) comparison showing the two layouts are identical.

Hand in a plot of your layout, the S-Edit schematics, the two spice files and the LVS output.

Simulation, done by November 7

B1

Extract your layout from Part A

B2

Simulate the spice file in TSPICE for a transient response to a step input.

Hand in the spice file and a plot of the transient response.

Padframe, preferably due November 14

C1

Insert the follower integrator in the pad frame.

C2

Draw a schematic of the follower integrator and padframe in S-EDIT.

C3

Do a LVS (Layout vs. schematic) comparison showing the two chip layouts are identical.

Hand in a plot of the chip layout, the S-EDIT schematics, the spice files and the LVS output.