EEL6935: HW#3

Due Thursday, October 10, 1996 in class. Note: We will have our first and only exam on October 17. It will be completely open book and open notes.

PART A: Design

You should solve 2 of the following 5 design problems. Any extra problems you solve will be extra credit. For each problem you solve, draw a schematic and explain why the circuit solves the problem. Explain any assumptions and limitations as necessary. Unless currents or voltages are not explicitly specified, you may specify whatever signal representations you like for inputs and outputs.

A1

Design a variation of a transamp that output a current that is linear in the input voltage difference for small values of but goes to zero for larger values of . (Hint: you may want to use one of the circuits you solved for your previous homeworks).

A2

Design a circuit that computes Ideally, the circuit should work for positive and negative values of as long as (Hint: you may want to try out translinear circuits).

A3

Design a circuit that computes the median of N input currents.

A4

Design a circuit that computes a low-pass filtered version of . This circuit might be useful for neural network computations where the values are the connection weights and represents the strength of the input neurons. Try to allow four-quadrant operations.

A5

Design a four-quadrant analog divider circuit. It should take two voltages as inputs and output a signal that represents the quotient of the two inputs.

PART B: Layout

B1

Layout a simple 5-transistor transamp in the CAD tool of your choice. Assume a 2um nwell technology with the standard scalable design rules listed in the book. Note, the layouts in the book, though functional, are not optimal. Try to keep transistors that should match as close as possible with current flowing in the same direction in each. Use 6x6um as minimum size transistor and make your current mirror transistors at least 18um long. Always keep power and ground lines in metal. Do not forget to include substrate and well contacts.

B2

Run a DRC check to make sure that you have no design rule errors.

B3

Add appropriate labels for VDD, GND, V1, V2, VB and VOUT.

B4

Extract your layout as a SPICE file and look at the file to make sure everything makes sense. Re-draw your schematic using the node labels from the spice file to make sure.

B5

(Optional) If you are using L-Edit take a look at a cross-section of your layout using the Cross-Section command under the Special menu.

For this part, you need to hand in the following:

• A printout of your layout
• A printout of the extracted SPICE file
• A drawn schematic on the SPICE printout showing the node labels for each transistor.

Some notes on Using L-EDIT

If you are using L-Edit on the eel system in Benton Lab. You should copy the following files from /homes/harris/tanner

• ledit.tdb the SCGA technology file for L-Edit This is the initial set up file that contains the color maps, layer names, design rules etc. for the SCGA technology.
• ledit.ext the extractor definition file.
• ledit.xst the cross-section tool setup file.
• ledit.elm the special-element description file.

You have to copy these files to the directory you are working in because there is some system problem with the installation that we have not yet figured out. If you want to look at a fully completed chip, take a look at /homes/harris/early/early.tdb

You should be able to do some simple layouts with the student edition of L-EDIT and load them into the Unix version. However, it is unlikely that you will be able to load Unix version layouts into the student version (because of version mismatch checks the software makes). The student version is also very limited-you will not be able to even load in our standard pad frame with the student version.

Note: As part of the next homework, we will draw a schematic and extract it in order to run an LVS (Layout Versus Schematic) comparison. We will then simulate the SPICE output.