EEL6935: Projects

EEL 6935  -  Fall 1996 Analog Signal Processing

Your final project consists of a significant portion of the grade in this class. Everyone must have a project idea by Friday, Thursday, November 7 (hopefully sooner). Important dates are as follows:

1. Thursday, October 31, In lieu of class, I will meet with each of you individually to discuss your final project idea.
2. By November 7, 5pm. Email me a description about your project (at least one paragraph in length).
3. By Thursday of each subsequent week each student must email a short description of your accomplishments for the week to Dr. Harris (harris@cnel.ufl.edu). If you have accomplished nothing for a particular week, send me a message stating this. You need not send a message on Thanksgiving.
4. by 5pm, Thursday, December 5, your final chip layout must be completed and mailed to Dr. Harris.
5. By 5pm, Tuesday, December 10. The final project reports must be turned in.

Your final grade for the project will be based on the on-time completion and quality of each of the above items.

Your final project report is due by 5pm Dec 10, 1996. It should be written as if it were to be submitted to a conference and therefore should contain the following components:

1. Literature review about the state of the art in the field.
2. A concise description of the problem and previous solutions.
3. A detailed description of your solution to the problem.
4. Algorithmic simulations (probably in MATLAB) showing the expected performance of your proposed solution.
5. Transistor level simulation (probably in SPICE) showing the proper operation of your circuit building blocks.
6. The appendix should contain complete documented schematics for the chip you are submitting. (Someone who knows nothing about your chip should be able to test your chip after reading your report) Any other aspects too detailed for main text should be placed in an appendix.

Your final chip layout in cif should be emailed to Dr. Harris by 5pm, Thursday December 5. Your final design should be extracted and compared against a netlist generated from a schematic (or even typed by hand). (Alternatively, you can show correctness by simulating an extracted version of the layout.) Funding for chip fabrication is limited to 1/2 of a MOSIS 40-pin 2mmx2mm TINY-CHIP for each student in the class. This means that the 40-pins must be split about the two partners. For most students this will not be a problem and makes the design of the padframe simpler since you will have someone to work with. However if your project demands a full tiny-chip talk with Dr. Harris to work out a solution.

Here is a list of rough project ideas. You do not have to choose one of these topics and are encouraged to come up with one of your own. Feel free to come to office hours or schedule an appointment with Dr. Harris to discuss your ideas.

• Circuits
  1. Bipolar circuits
  2. Translinear circuits
  3. Large time constants/capacitance multipliers
  4. Floating-gate learning
  5. Compact low-precision A/D or D/A converters
• Physics
  1. Linear/non-linear dynamical system models
  2. Linear equation solver
  3. Silicon neural networks
  4. Circuits that exhibit chaos
  5. Echo/Noise cancellation
• Vision
  1. Photoreceptors
  2. Biological models of adaptation in the visual system
  3. Image Processing (motion, edges, depth, etc.)
• Auditory
  1. Speech generation/preprocessing
  2. Autogain circuit for auditory signals
  3. Cochlea models
  4. Auditory Localization
• Neurons
  1. Realistic models of biological neurons